The DDR, DDR2 and DDR3 memories have been based on the design of SDRAM or Synchronous Dynamic Random Access Memory. This means that they make use of the clock signal to synchronize things. DDR can be termed as Double Data Rate which implies that the memories transfer two data chunks per clock cycle. In this way they are able to achieve double the performance of memories. Even the memories are labeled with double the real maximum clock rate that they can operate with. The DDR-800 memories can work at 400MHz. The DDR2-1066 and DDR-1066 memories at 533MHz and the DDR3-1333 memories at 666.6 MHz and so on.
These clock rates are the maximum that the memory can use in the official sense. While installing a DDR2-1066 memories on the computer which can access the memory subsystem at 400MHz or 800 MHz DDR the memories would be accessible at 400 MHz or 800 MHz DDR and not at 533 MHz or 1066 MHz DDR. This is possible as the clock signal has a memory controller that is a circuit situated outside the memory. It could be located in the north bridge chip from the motherboard or it could be embedded inside the CPU. This depends on the type of system.
We name the system DDRx-yyyy (x meaning the technology generation and yyyy the DDR clock rate) for the memory chips. The memory modules located on the little printed board where the memory chips are soldered into use another naming system PCx-zzzz. X is the technology generation and zzzz is the maximum bandwidth.
By this process we can find out how many bytes can be transferred per second between the memory controller and the memory module. This is based on the assumption that the data will get transferred on every single clock pulse. In order to arrive at the maximum theoretical transfer rate in MB/s i.e megabytes per second we can multiply the DDR clock in MHz by eight. For instance the DDR2-800 memories would have a maximum theoretical rate of 6400 MB/s by following the maths 800×8. The memory modules that use this kind of memory are called PC2-6400. These numbers can be understood as maximum theoretical numbers that can be never reached. It is because it doesn't really happen that the memory sends data to the memory controller every single clock cycle. It is important that the memory controller and the memory exchange their commands of instructing the memory to deliver data stored at a stated position. It is during such time that the memory won't transfer the data.